(1) Field of the Invention
This invention relates to improved recessed gate field effect transistor devices and methods of making, and more particularly to metal oxide semiconductor (MOS) field effect transistors with recessed gates that are fabricated with the use of self-aligned source and drain regions and recessed oxide technology.
(2) Description of the Prior Art
In semiconductor manufacturing, the cost of semiconductor devices is directly related to the number and size of devices, and their related functions, which can be placed on a single semiconductor chip. Also, affecting the cost is the number and complexity of the manufacturing steps needed to fabricate the integrated circuit devices.
Initially, efforts to increase device density was limited primarily by photolithographic dimensional limitations. Subsequently, techniques have become available which enable dimensions of less than one micron to be used in photolithographic processing. Semiconductor processing techniques which reduce the number of processing steps and/or their complexity are also useful to lower the cost of semiconductor devices by increasing product yield or by increasing density, when the number of critical mask alignment steps can be reduced.
In the manufacture of MOSFET integrated circuit devices, however, a reduction in size, achievable with newer photolithographic techniques, presented other formidable problems. When the size of the conventional MOS FET device structure where the source, drain, and gate regions are all spaced along a planar surface the threshold voltage is reduced. Reduction of the threshold voltage results in punch through. A well known scaling method is effective to improve the aforementioned problems. This method dictates reduction of the supply voltage and also an increase of the substrate density. Reduction of the supply voltage leads to reduction of the margin concerning the electric noise and fluctuations of the threshold voltage. Increasing the substrate density is likely to result in increased current leakage in the sub-threshold region. The significance of these problems is increased as integration density is increased.
A MOS field effect transistor device structure that seeks to increase the effective length of the channel length is shown in U.S. Pat. No. 4,455,740 where a groove is formed between the source and drain and the gate insulation and gate electrode place in the groove. However, the fabrication requires a complex fabrication process.